DaddleDew@lemmy.world to PC Master Race@lemmy.worldEnglish · edit-22 months agoIt's evolving, but backwardslemmy.worldimagemessage-square41fedilinkarrow-up1418arrow-down114file-text
arrow-up1404arrow-down1imageIt's evolving, but backwardslemmy.worldDaddleDew@lemmy.world to PC Master Race@lemmy.worldEnglish · edit-22 months agomessage-square41fedilinkfile-text
minus-squareyetAnotherUser@discuss.tchncs.delinkfedilinkEnglisharrow-up4·edit-22 months agoThe issue with that design is that the PCIe standard would be replaced with something proprietary.
minus-squaregrue@lemmy.worldlinkfedilinkEnglisharrow-up1·2 months agoIt would be connected via Infinity Fabric, just like Epyc CPUs in dual-socket boards, as well as the interconnect between CPU and GPU chiplets in APUs, already are. Why would that be bad?
The issue with that design is that the PCIe standard would be replaced with something proprietary.
It would be connected via Infinity Fabric, just like Epyc CPUs in dual-socket boards, as well as the interconnect between CPU and GPU chiplets in APUs, already are. Why would that be bad?